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15 v/12 v quad spst switches adg1311/adg1312/adg1313 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005C2009 analog devices, inc. all rights reserved. features 33 v supply range fully specified at +12 v, 15 v 130 on resistance no v l supply required 3 v logic-compatible inputs rail-to-rail operation 16-lead tssop and 16-lead soic typical power consumption: <0.03 w applications signal switching battery-powered systems communication systems audio/video signal routing functional block diagram in1 in2 in3 in4 s1 d1 s2 d2 s3 d3 s4 d4 adg1311 switches shown for a logic 1 input in1 in2 in3 in4 s1 d1 s2 d2 s3 d3 s4 d4 adg1312 in1 in2 in3 in4 s1 d1 s2 d2 s3 d3 s4 d4 adg1313 05676-001 figure 1. general description the adg1311/adg1312/adg1313 are monolithic cmos devices containing four independently selectable switches designed on a cmos process. the adg1311/adg1312/adg1313 contain four independent single-pole/single-throw (spst) switches. the adg1311 and adg1312 differ only in that the digital control logic is inverted. the adg1311 switches are turned on with logic 0 on the appro- priate control input, while logic 1 is required for the adg1312. the adg1313 has two switches with digital control logic similar to the adg1311; the logic is inverted on the other two switches. the adg1313 exhibits break-befo re-make switching action for use in multiplexer applications. each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. in the off condition, signal levels up to the supplies are blocked. product highlights 1. 3 v logic-compatible digital inputs: v ih = 2.0 v, v il = 0.8 v. 2. no v l logic power supply required. 3. 16-lead tssop and soic packages.
adg1311/adg1312/adg1313 rev. a | page 2 of 12 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? specifications ..................................................................................... 3 ? dual supply ................................................................................... 3 ? single supply ................................................................................. 4 ? absolute maximum ratings ............................................................5 ? esd caution...................................................................................5 ? pin configuration and function descriptions ..............................6 ? terminology .......................................................................................7 ? typical performance characteristics ..............................................8 ? test circuits ..................................................................................... 10 ? outline dimensions ....................................................................... 12 ? ordering guide .......................................................................... 12 ? revision history 2/09rev. 0 to rev. a changes to power requirements, i dd , digital inputs = 5 v parameter, table 1 ............................................................................. 3 changes to power requirements, i dd , digital inputs = 5 v parameter, table 2 ............................................................................. 4 10/05revision 0: initial version
adg1311/adg1312/adg1313 rev. a | page 3 of 12 specifications dual supply v dd = 15 v 10%, v ss = ?15 v 10%, gnd = 0 v, unless otherwise noted. table 1. y version 1 parameter 25c ?40c to +105c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance (r on ) 130 230 typ v s = 10 v, i s = ?1 ma; see figure 10 200 max v dd = +13.5 v, v ss = ?13.5 v on resistance match between channels (?r on ) 5 typ v s = 10 v, i s = ?1 ma 10 max on resistance flatness (r flat(on) ) 25 typ v s = ?5 v/0 v/+5 v; i s = ?1 ma 65 max leakage currents v dd = +16.5 v, v ss = ?16.5 v source off leakage, i s (off ) 10 na typ v s = 10 v, v d = ? 10 v; see figure 11 drain off leakage, i d (off ) 10 na typ v s = 10 v, v d = ? 10 v; see figure 11 channel on leakage, i d , i s (on) 10 na typ v s = v d = 10 v; see figure 12 digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max digital input capacitance, c in 2.5 pf typ dynamic characteristics 2 t on 105 ns typ r l = 300 , c l = 35 pf 125 180 ns max v s = 10 v; see figure 13 t off 40 ns typ r l = 300 , c l = 35 pf 50 60 ns max v s = 10 v; see figure 13 break-before-make time delay, t d 25 ns typ r l = 300 , c l = 35 pf (adg1313 only) 10 ns min v s1 = v s2 = 10 v; see figure 14 charge injection 2 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 15 off isolation 80 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 16 channel-to-channel crosstalk 90 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 17 ?3 db bandwidth 600 mhz typ r l = 50 , c l = 5 pf; see figure 18 c s (off ) 5 pf typ c d (off ) 5 pf typ c d , c s (on) 10 pf typ power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 0.001 a typ digital inputs = 0 v or v dd 1.0 a max i dd 220 a typ digital inputs = 5 v 380 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1.0 a max i ss 0.001 a typ digital inputs = 5 v 1.0 a max 1 temperature range for y version is ? 40c to +105c. 2 guaranteed by design, not subject to production test.
adg1311/adg1312/adg1313 rev. a | page 4 of 12 single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 2. y version 1 parameter 25c ?40c to +105c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on ) 325 520 typ v s = 0 v ? 10 v, i s = ?1 ma; see figure 10 500 max v dd = 10.8 v, v ss = 0 v on resistance match between channels (?r on ) 10 typ v s = 0 v ? 10 v, i s = ?1 ma 15 max on resistance flatness (r flat(on) ) 65 typ v s = 3 v/6 v/9 v, i s = ?1 ma leakage currents v dd = 13.2 v, v ss = 0 v source off leakage, i s (off ) 10 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 11 drain off leakage, i d (off ) 10 na typ v s = 1 v/10 v, v d = 10 v/1 v see figure 11 channel on leakage, i d , i s (on) 10 na typ v s = v d = 1 v or 10 v; se e figure 12 digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.001 a typ v in = v inl or v inh 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 2 t on 120 ns typ r l = 300 , c l = 35 pf 155 210 ns max v s = 8 v; see figure 13 t off 45 ns typ r l = 300 , c l = 35 pf 65 80 ns max v s = 8 v; see figure 13 break-before-make time delay, t d 50 ns typ r l = 300 , c l = 35 pf (adg1313 only) 10 ns min v s1 = v s2 = 8 v; see figure 14 charge injection 2 pc typ v s = 6 v, r s = 0 , c l = 1 nf; see figure 15 off isolation 80 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 16 channel-to-channel crosstalk 90 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 17 ?3 db bandwidth 500 mhz typ r l = 50 , c l = 5 pf; see figure 18 c s (off ) 5 pf typ c d (off ) 5 pf typ c d , c s (on) 10 pf typ power requirements v dd = 13.2 v i dd 0.001 a typ digital inputs = 0 v or v dd 1.0 a max i dd 220 a typ digital inputs = 5 v 380 a max 1 temperature range for y version is ? 40c to +105c. 2 guaranteed by design, not subject to production test.
adg1311/adg1312/adg1313 rev. a | page 5 of 12 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v dd to v ss 35 v v dd to gnd ?0.3 v to +25 v v ss to gnd +0.3 v to ?25 v analog inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first digital inputs 1 gnd ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, s or d 100 ma (pulsed at 1 ms, 10% duty cycle max) continuous current per channel, s or d 25 ma operating temperature range automotive ?40c to +105c storage temperature range ?65c to +150c junction temperature 150c 16-lead tssop, ja thermal impedance (4-layer board) 112c/w 16-lead soic, ja thermal impedance 77c/w reflow soldering peak temperature, pb free 260c 1 overvoltages at in, s, or d are clamped by internal diodes. current should be limited to the maximum ratings given. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 4. adg1311/adg1312 truth table adg1311 inx adg1312 inx switch condition 0 1 on 1 0 off table 5. adg1313 truth table adg1313 inx switch 1, 4 switch 2, 3 0 off on 1 on off esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adg1311/adg1312/adg1313 rev. a | page 6 of 12 pin configuration and fu nction descriptions top view 1 2 3 4 5 6 7 8 adg1311/ adg1312/ adg1313 nc = no connect 16 15 14 13 12 11 10 9 d1 s1 v ss d4 s4 gnd in1 d2 s2 v dd d3 in4 in3 s3 nc in2 05676-002 figure 2. soic/tssop pin configuration table 6. pin function descriptions pin no. neonic description 1 in1 logic control input. 2 d1 drain terminal. can be an input or output. 3 s1 source terminal. can be an input or output. 4 v ss most negative power supply potential. 5 gnd ground (0 v) reference. 6 s4 source terminal. can be an input or output. 7 d4 drain terminal. can be an input or output. 8 in4 logic control input. 9 in3 logic control input. 10 d3 drain terminal. can be an input or output. 11 s3 source terminal. can be an input or output. 12 nc no connection. 13 v dd most positive power supply potential. 14 s2 source terminal. can be an input or output. 15 d2 drain terminal. can be an input or output. 16 in2 logic control input.
adg1311/adg1312/adg1313 rev. a | page 7 of 12 terminology i dd the positive supply current. i ss the negative supply current. v d (v s ) the analog voltage on terminal d and terminal s. r on the ohmic resistance between d and s. r flat(on) flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified analog signal range. i s (off) the source leakage current with the switch off. i d (off) the drain leakage current with the switch off. i d , i s (on) the channel leakage current with the switch on. v inl the maximum input voltage for logic 0. v inh the minimum input voltage for logic 1. i inl (i inh ) the input current of the digital input. c s (off) the off switch source capacitance, measured with reference to ground. c d (off) the off switch drain capacitance, measured with reference to ground. c d , c s (on) the on switch capacitance, measured with reference to ground. c in the digital input capacitance. t on the delay between applying the digital control input and the output switching on. see figure 13 . t off the delay between applying the digital control input and the output switching off. see figure 13 . charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching. off isolation a measure of unwanted signal coupling through an off switch. crosstalk a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. bandwidth the frequency at which the output is attenuated by 3 db. on response the frequency response of the on switch. insertion loss the loss due to the on resistance of the switch.
adg1311/adg1312/adg1313 rev. a | page 8 of 12 typical performance characteristics v dd = +15v v ss = ?15v source or drain voltage (v) on resistance ( ) 200 180 160 140 120 100 60 80 0 20 40 ?15 ?12 ?9 ?6 ?3 3 9 0 6 12 15 05676-008 t a = 25 c figure 3. on resistance as a function of v d (v s ) for dual supply source or drain voltage (v) on resistance ( ) 450 400 350 300 250 150 200 0 50 100 02468101 05676-005 2 v dd = 12v v ss = 0v t a = 25 c figure 4. on resistance as a function of v d (v s ) for single supply source or drain voltage (v) on resistance ( ) 250 150 200 0 50 100 ?15 ?10 ?5 0 5 10 15 05676-006 v dd = +15v v ss = ?15v t a = +25 c t a = +85 c t a = ?40 c figure 5. on resistance as a function of v d (v s ) for different temperatures, dual supply source or drain voltage (v) on resistance ( ) 600 400 500 300 200 0 100 02468101 05676-007 2 v dd = 12v v ss = 0v t a = +25 c t a = +85 c t a = ?40 c figure 6. on resistance as a function of v d (v s ) for different temperatures, single supply temperature (c) time (ns) 200 160 180 140 100 60 20 120 80 40 0 ?40 ?20 40200 60 80 100 120 05676-016 15v ds t off 12v ss t off 15v ds t on 12v ss t on figure 7. t on /t off times vs. temperature frequency (hz) off isolation (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 10k 100k 1m 10m 100m 1g 05676-017 v dd = +15v v ss = ?15v t a = 25 c figure 8. off isolation vs. frequency
adg1311/adg1312/adg1313 rev. a | page 9 of 12 frequency (hz) crosstalk (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?120 ?110 10k 100k 1m 10m 100m 05676-018 v dd = +15v v ss = ?15v t a = 25 c figure 9. crosstalk vs. frequency
adg1311/adg1312/adg1313 rev. a | page 10 of 12 test circuits i ds v1 sd v s r on = v1/i ds 05676-020 sd v s a a v d i s (off) i d (off) 05676-021 sd a v d i d (on) nc nc = no connect 05676-022 figure 10. on resistance figure 11. off leakage figure 12. on leakage v s in sd gnd r l 300 c l 35pf v out v dd v ss 0.1 f v dd 0.1 f v ss adg1312 adg1311 v in v in v out t on t off 50% 50% 90% 90% 50% 50% 05676-023 figure 13. switching times v s2 in1, in2 s2 d2 v s1 s1 d1 gnd r l 300 c l 35pf v out2 v out1 v dd v ss 0.1 f v dd 0.1 f v ss v in v out1 v out2 adg1313 t d t d 50% 50% 90% 90% 90% 90% 0v 0v 0v r l 300 c l 35pf 05676-024 figure 14. break-before-make time delay in v out adg1312 adg1311 v in v in v out off v out on q inj = c l v out sd v dd v ss v dd v ss v s r s gnd c l 1nf 05676-025 figure 15. charge injection
adg1311/adg1312/adg1313 rev. a | page 11 of 12 v out 50 network analyzer r l 50 in v in s d 50 off isolation = 20 log v out v s v s v dd v ss 0.1 f v dd 0.1 f v ss gnd 05676-026 figure 16. off isolation channel-to-channel crosstalk = 20 log v out gnd s1 d2 s2 v out network analyzer r l 50 r 50 v s v s v dd v ss 0.1 f v dd 0.1 f v ss 05676-027 figure 17. channel-to-channel crosstalk v out 50 network analyzer r l 50 in v in s d insertion loss = 20 log v out with switch v out without switch v s v dd v ss 0.1 f v dd 0.1 f v ss gnd 05676-028 figure 18. bandwidth
adg1311/adg1312/adg1313 rev. a | page 12 of 12 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 19. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-ac 10.00 (0.3937) 9.80 (0.3858) 16 9 8 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 1.27 (0.0500) bsc seating plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarity 0.10 8 0 060606-a 45 figure 20. 16-lead standard small outline package [soic_n] narrow body (r-16) dimensions shown in millimeters and (inches) ordering guide model temperature range packag e description package option ADG1311YRUZ 1 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 ADG1311YRUZ-reel7 1 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 adg1311yrz 1 ?40c to +105c 16-lead narrow body small outline package [soic_n] r-16 adg1311yrz-reel7 1 ?40c to +105c 16-lead narrow body small outline package [soic_n] r-16 adg1312yruz 1 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 adg1312yruz-reel7 1 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 adg1312yrz 1 ?40c to +105c 16-lead narrow body small outline package [soic_n] r-16 adg1312yrz-reel7 1 ?40c to +105c 16-lead narrow body small outline package [soic_n] r-16 adg1313yruz 1 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 adg1313yruz-reel7 1 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 adg1313yrz 1 ?40c to +105c 16-lead narrow body small outline package [soic_n] r-16 adg1313yrz-reel7 1 ?40c to +105c 16-lead narrow body small outline package [soic_n] r-16 1 z = rohs compliant part. ?2005C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05676-0-2/09(a)

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